1. Field of the Invention
The present invention relates to a power semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
Generally, power semiconductor devices (for example, power MOSFETs (metal oxide semiconductor field-effect transistors) or IGBTs (insulated gate bipolar transistors)) are manufactured in a trench or planar type. Planar-type power semiconductor devices are used for switching-mode power supplies, DC-DC converters, electronic stabilizers for fluorescent lamps, inverters for motors, and others. They are required to have small switching/conduction loss and a sufficiently high break-down voltage. The use of these devices enables to reduce the size of final products due to higher energy efficiency and less heat generation, thereby achieving less consumption of resources.
In planar-type power semiconductor devices, unit cells are formed in a polygonal shape to increase a channel density per unit area, thereby leading to reduced drain-source on-resistance (Rds(ON)). However, expendation type of the depletion area is spherical, when a high voltage is applied between a source and a drain in a turn-off state of the devices, a break-down voltage is unfavorably reduced.
In order to increase the break-down voltage of planar-type power semiconductor devices, it is necessary to increase the thickness and specific resistance of an epitaxial region, which inevitably increases drain-source on-resistance (Rds(ON)). As such, there exists a trade-off relation between drain-source on-resistance (Rds(ON)) and break-down voltage in planar-type power semiconductor devices, and thus, it is necessary to improve the structure of planar-type power semiconductor devices considering such a trade-off relation.
Meanwhile, planar-type power semiconductor devices are classified into a closed cell-type and a stripe-type.
In closed cell-type power semiconductor devices, a junction type between a P type conductive region and an N type epitaxial layer is approximately sphere surface, and thus, an Avalanche break-down voltage is decreased in an active region. In addition, a gate polysilicon layer and an N type epitaxial layer (drain-side drift region) face each other over a large area, which increases Miller capacitance. Therefore, a switching speed is lowered, and when high dVDS/dt is applied, a malfunction easily occurs.
In stripe-type power semiconductor devices, a junction type between a P type conductive region and an N type epitaxial layer is approximately cylinder surface, and thus, an Avalanche break-down voltage is increased in an active region. In addition, a gate polysilicon layer and an N type epitaxial layer (drain-side drift region) face each other over a small area, which decreases Miller capacitance. Therefore, a switching speed is increased, and when high dVDS/dt is applied, a malfunction is less likely to occur. In this regard, stripe-type power semiconductor devices have now been mainly manufactured, sold, and used.
Meanwhile, in both closed cell-type and stripe-type power semiconductor devices, gate signals are transmitted in all directions (e.g., up-/down-ward/right-/left-ward), and thus, there exists serious deviation in the transmission speed of the gate signals and the impedance of a gate driver circuit, among device elements.
In this regard, stripe-type power semiconductor devices are required to form gate bus lines using the same material as a source metal layer to connect gate polysilicon layers, which causes area loss and poor flow of a source current, thereby resulting in device degradation.